library verilog;
use verilog.vl_types.all;
entity minus_4 is
    port(
        x               : in     vl_logic_vector(3 downto 0);
        y               : in     vl_logic_vector(3 downto 0);
        \out\           : out    vl_logic_vector(3 downto 0);
        CF              : out    vl_logic;
        enable          : in     vl_logic
    );
end minus_4;
